1. Field of the Invention
The present invention relates to a low voltage SOI (Silicon On Insulator) logic circuit using a SOI field effect transistor operable by 1 V dry battery.
2. Description of Related Art
As a conventional low voltage logic circuit, one such as shown in FIG. 1 is known. The logic circuit employs a bulk CMOS circuit and is disclosed in Japanese patent application laying open No. 6-29834 (1994), and S. Mutoh, et al. "1 V HIGH SPEED DIGITAL CIRCUIT TECHNOLOGY WITH 0.5 .mu.m MULTI-THRESHOLD CMOS", IEEE, 1993, pages 186-189.
This circuit has a basic arrangement, in which a CMOS logic circuit group 3 is connected between a power switching MOSFET 4 and a power switching MOSFET 5 which are connected to a high potential power supply line 1 and a low potential power supply line 2, respectively. Here, the power switching MOSFETs 4 and 5 are MOSFETs with high threshold voltage, and the logic circuit group 3 is composed of low threshold voltage MOSFETs.
The high threshold voltage power switching MOSFETs 4 and 5 are provided with a sleep signal SL and its inverted signal *SL at the gates thereof, respectively. The MOSFETs 4 and 5 are kept nonconducting by a high level signal SL in a sleep mode (during a waiting time period) of the logic circuit group 3, thereby stopping power supply to the logic circuit group 3. Reversely, the power is supplied to the logic circuit group 3 in an active mode by keeping the sleep signal SL low, thereby maintaining the MOSFETs 4 and 5 in a conducting state.
Generally, although low threshold voltage MOSFETs have characteristics of high speed operation, their leakage current in a nonconducting state is large. In contrast, although high threshold voltage MOSFETs have characteristics of low speed operation, their leakage current in a nonconducting state is small. Therefore, the circuit as shown in FIG. 1 can operate at a high speed in the active mode of the logic circuit group 3 while maintaining a small leakage current in the sleep mode.
It should be noted here that individual substrates of MOSFETs of the logic circuit group 3 are connected to the high potential power supply line 1 or the low potential power supply line 2 in the conventional low voltage logic circuit. This substrate bias is applied for preventing faulty operations due to latch up which will readily occur in bulk CMOS. Incidentally, although the substrates of MOSFETs of the logic circuit group of FIG. 1 of the above-mentioned paper of Mutoh, et al. are shown as though they were not connected to any points, this is for the simplicity of drawing, and the substrates of these MOSFETs are actually connected to respective power supply lines.
Applying such construction to a SOI CMOS logic circuit presents a problem that a device area will increase. This will be described below.
FIG. 2 is a cross-sectional view showing the structure of a conventional SOI MOSFET. A buried oxide 12 is formed on a silicon substrate 11, and an active region 13 consisting of a single crystal silicon layer is built on the buried oxide 12. The active region 13 consists of a source 131, a drain 132 and a body 132 sandwiched between them. The active region 13 is covered with a gate oxide 14, and a gate electrode 15 is formed on the gate oxide 14. By applying a voltage on the gate electrode 15, a channel 134 is formed in the top portion of the body 133. Thus, the active region 13 consists of the source 131, the drain 132 and the body 133, and the body 133 is insulated from the silicon substrate 11 by the buried oxide 12.
FIG. 3A shows a method of applying a bias to the substrate of a bulk MOSFET, and FIG. 3B shows a method of applying a bias to the body of a SOI MOSFET. In the bulk PMOSFET as shown in FIG. 3A, an N well 20 is built in the substrate, a P+ source 21 and a P+ drain 22 are formed therein, and a gate electrode 23 is formed on the top surface of the well 20 via a gate oxide. In addition, an N+ bias region 24 is formed in the well 20 in such a fashion that a potential is applied thereto through contacts 25 from the top of the silicon.
On the other hand, since the body 133 is insulated from the silicon substrate 11 as shown in FIG. 2 in a SOI PMOSFET shown in FIG. 3B, the body 133 must be extended via a connecting portion 34A to a bias region 34, in which contacts 35 are formed.
As a result, the area of the bias region increases in the SOI MOSFET as compared with the bulk MOSFET, so that the SOI MOSFET has a disadvantage that its occupied area increases by that amount. In particular, an increase in size of MOSFETs constituting the logic circuit group 3 poses a problem that it will increase the whole circuit area, and hence, reduce the degree of integration.